EducationQuantum dot transistor - Explanation, application, researches

Quantum dot transistor – Explanation, application, researches

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Quantum dot single electron transistor have the same function as the traditional transistor but working in a different way.
At the central position of the transistor(between Drain, Gate and Source) there are many dots which only allow to electrons flow under a certain voltage. This voltage is controlled by the Gate at the two sides of the quantum dots. To prepare such semiconductor We have to go through several steps.

  1. Surface preparation, prepare a clean circle then cover the surface with the hydrogen atom which will avoid the surface of the silicon to reach with another atoms,
  2. STM hydrogen lithography, to remove the hydrogen from the surface. STM tip removes hydrogen atoms from the silicon surface to produce chemically reactive patterns,
  3. Gas phase doping, improve the conductance of the semiconductor. Dopant precursor molecules chemically react with in the patterned area. After heating the dopands are incorporated into the silicon lattice and the STM desorbed hydrogen patter is transferred to a doping pattern.
  4. Silicon encapsulation, cover with the another silicon levels to protect the central position of the semiconductor. Transmission Electron Microscopy reveals the highly ordered crystallinity of the epitaxial sillicon overgrowth.

The quantum dot in single electron transistor is more conductive and more accurate than in the traditional transistor.

What are quantum dots

Quantum dots are tiny, man-made structures, each smaller than 1 micron (μm) across. These structures are usually between 10 and 100 nanometers (nm) in size. A quantum dot contains about 100,000 to 100 million atoms, creating a unique electronic structure. They’re often called artificial atoms, molecules, or crystals because of their engineered nature.

Quantum dots behave differently from larger solid crystals. This difference is mainly due to quantization, a phenomenon greatly influenced by the size of the quantum dot. As a result, they have special physical traits not found in bigger materials.

quantum dots
Figure 1: Quantum dot. Credit:

The electronic properties of quantum dots can be significantly changed. This is possible by altering their chemical make-up, shape, or by using external forces like electric and magnetic fields, or mechanical pressure. This flexibility makes them useful for a wide range of purposes.

There are various types of quantum dots, each with its own properties and uses. These include:

  • Nanocrystals embedded in an insulating matrix,
  • Nanoparticles contained within porous materials,
  • Self-organized quantum dots,
  • Quantum dots within semiconductor heterostructures,
  • Electrostatically defined quantum dots.

Each type has specific advantages and potential applications, based on their composition and how they are made. This variety highlights the versatility and broad use of quantum dots in different tech and scientific areas.

Quantum dots in semiconductor heterostructures controlled by gate voltages

Schematic of a vertical three-electrode nanowire system
Figure 2: Schematic of a vertical three-electrode nanowire system. Credit:

A quantum dot system is like a network made up of tunnel resistors and capacitors. Let’s look at a single quantum dot to understand this better. The quantum dot, or QD, connects with source (S) and drain (D) contacts. It does this through tunneling barriers, which are like a mix of a tunnel resistor and a capacitor. This is shown in the related diagram.

Also, the quantum dot is connected to a gate electrode by a capacitor (CG). This setup lets us apply a gate voltage (VG), which is key to adjusting the system’s electricity. Because quantum dots are so small, the energy inside them forms a distinct pattern. This pattern comes from quantum mechanics, which rules how things work at this tiny scale.

This distinct energy pattern sets quantum dots apart from bulk materials, where energy levels are usually continuous. By changing the gate voltage, we can precisely adjust the quantum dot’s electronic features. This makes these systems very flexible for different uses, like in quantum computing or advanced sensors. The interaction among the tunnel resistors, capacitors, and the quantum dot’s unique qualities is vital to how these tiny structures work and what they can be used for.

Electrostatic quantum dots

Schematic illustration of an electrostatic quantum dot
Figure 3: Schematic illustration of an electrostatic quantum dot. The motion of an electron in a two-dimensional electron gas is limited by specific potentials derived from the gates of the quantum. Credit:

In quantum dot systems controlled by electrostatics, we trap electrons using an electrostatic field. This field comes from voltages applied to the wires connected to the tiny device. By changing the shape of the device, we can create different types of trapping areas, or ‘confinement potentials’, each with its own features.

Designing these devices involves careful planning to get the right kind of trapping area. These can range from a simple box-like shape to one with more gradual edges. By experimenting with the device’s design, we can make a trapping area that looks like a bell curve (Gaussian shape). In other setups, we can create a parabolic, or U-shaped, trapping area over a large part of the quantum dot.

Being able to change the shape of this trapping area is key to determining how the quantum dot works electronically. The shape affects the energy levels and how electrons are arranged inside the quantum dot. By customizing these trapping areas, we can tailor quantum dots for specific uses, like in quantum computing or tiny sensing devices. This flexibility in design highlights the room for creativity and advancement in quantum dot technology.

Quantum dot transistor

When building quantum dot field-effect transistors (FETs), two main setups are usually used. The first one is called the bottom-gate configuration. In this setup, a highly doped silicon wafer acts as the gate, and it’s separated from the quantum dot (QD) film by a layer of silicon dioxide (SiO2), which is an insulating material. The source and drain electrodes are placed on this setup, made using either pre-patterning with optical lithography and metal evaporation or post-patterning using shadow mask evaporation techniques. The QD film is then added to the substrate using methods like drop casting or spin coating.

The second setup is the top-gate configuration. Here, after putting the electrodes and the QD films in place, another layer of insulating material is added on top. This layer can be made of SiO2, Al2O3, or ion gels. Its job is to insulate the top gate electrode from the QD film underneath. In this setup, during measurements, voltage is applied to both the gate and the drain, while the source is grounded to create an electronic flow.

Basic configurations of QD based field-effect transistors (FET)
Figure 4: Basic configurations of QD based field-effect transistors (FET): (a) bottom-gate FET; (b) top-gate FET. L and W show transistor channel length and width, respectively. S, D, and G are the source, drain, and gate electrodes (terminals). Credit: American Chemical Society.

Silicon substrate-based FETs are commonly used for testing materials because they are reliable and well-known. But there’s growing interest in FETs made with polymer substrates. Research shows that these polymer substrate FETs are useful for testing and also show a lot of promise for using QDs to create electronic circuits on flexible, cost-effective materials. Moreover, these developments highlight the benefit of using low temperatures in making quantum dot FETs, which is important for advancing flexible and wearable electronic technologies.

Principle of FET operation

In the operation of a quantum dot field-effect transistor (QD FET), the application of a voltage between the source and the gate results in the injection and accumulation of charges at the interface between the semiconductor and the insulator. When this applied voltage surpasses a certain threshold value, denoted as VT, it leads to the formation of a conducting channel. Subsequent application of a bias across the source and drain terminals initiates a current flow from the drain to the source, referred to as IDS.

In scenarios where the drain voltage remains relatively low, the value of IDS​ shows a direct and linear relationship with the drain voltage. This characteristic behavior of the FET in this state is recognized as the linear regime of operation. In this regime, the relationship between the current and voltage is governed by a simplified equation that reflects the linear correlation between these two parameters. This simplified current-voltage relationship is crucial in understanding the fundamental operational mechanics of a QD FET and in predicting its behavior under various electrical inputs. The linear regime provides essential insights into the efficiency and potential applications of QD FETs in various electronic devices and systems.

Here, W and L represent the width and length of the channel, respectively. The field-effect mobility in the linear regime is denoted as μlin, a key parameter indicating how quickly charges move through the transistor channel under an electric field. Another important factor is the capacitance density (Ci) of the gate insulator, which is a measure of the gate insulator’s ability to store electric charge, expressed per unit area. Additionally, VG and VD are the gate and drain voltages, respectively, which are pivotal in controlling the transistor’s operation.

When the drain voltage (VD) exceeds the value of VG−VT (where VT is the threshold voltage), a phenomenon known as channel pinch-off occurs. In this state, the free charge density near the drain contact diminishes, approaching zero but not quite reaching it. This condition is critical in the transistor’s operation, marking the transition from the linear to the saturation regime.

In the saturation regime, any further increase in the drain voltage does not correspond to an increase in the drain current (IDS). This saturation of current is a defining characteristic of the FET in this operational state. The expression of current in the saturation regime is governed by a different set of equations that account for the non-linear relationship between IDS, VG, and VD under these conditions. Understanding these relationships is essential for optimizing the performance of QD FETs in various applications, particularly where precise control of current and voltage is required.

The current is then given by:

Both the equations referred to as Formula 1 and Formula 2 necessitate the knowledge of the gate insulator’s capacitance density, symbolized as Ci. The capacitance density is a critical factor in the extraction of mobility values from these formulas. It is calculated using a specific formula that considers the physical and dielectric properties of the gate insulator material. This calculation of Ci is not just a routine step; it is pivotal in determining the efficiency and responsiveness of the QD FET under various operational conditions.

The accurate determination of Ci is essential for the precise calculation of the mobility values in both the linear and saturation regimes of the QD FET. These mobility values, in turn, are key indicators of the transistor’s performance, influencing how effectively it can modulate electronic signals in various applications. Thus, the calculation of Ci and its incorporation into the mathematical models of QD FET operation are fundamental to the effective design and utilization of these semiconductor devices.

The calculation of the capacitance density Ci necessitates the inclusion of the gate dielectric thickness d, as well as the static permittivity ε of the dielectric material. The selection of gate dielectrics in QD FETs is influenced by developments in organic FETs and the ongoing search for high-permittivity dielectrics in the CMOS industry, particularly as gate dielectric thicknesses approach their physical limits.

Various materials, including some refractory ones with high permittivity values, have been explored for gate dielectrics in QD FETs. However, as highlighted by Robertson, issues such as film crystallinity can limit the practical application of these materials. Ion gels, known for generating high polarization, present challenges in fabrication within FET gate structures, particularly concerning compatibility with mass manufacturing techniques.

At present, a practical and potentially commercializable approach involves the use of an Al2O3 gate dielectric. To further enhance this configuration, especially when dealing with leakage current and moisture sensitivity, a surface monolayer of alkylphosphonic acid or alkylchlorosilane can be applied. Nonetheless, the development of new gate dielectric materials is a continuous process, and more advanced solutions may emerge in the future.

Key performance metrics for QD FETs include field-effect mobility, current on-to-off ratio, threshold voltage (VT), and sub-threshold slope (SS). In crystalline inorganic semiconductors, charge transport occurs in a delocalized manner, with phonon or impurity scattering being the main limiting factors for field-effect mobility. In contrast, QD films exhibit relatively weak inter-dot coupling due to long-chain synthesis ligands. Even though shorter ligands can enhance this coupling, it remains insufficient for true band-like transport akin to that observed in silicon. Consequently, charge carriers in QD films are highly localized, moving between dots primarily through tunneling or thermally assisted hopping.

The field-effect mobility in QD films is thus influenced by factors like inter-dot distance, temperature, and the distribution of trap states. The threshold voltage VT is indicative of the point where most deep traps are filled, allowing for meaningful charge transport. Therefore, VT reflects the initial concentration of charge carriers in the film, with a lower VT suggesting a higher doping level of the QD film. The sub-threshold slope (SS) is derived from these considerations, factoring in the intricacies of charge transport and trap states in QD FETs.

Steep sub-threshold slope (SS) is a highly advantageous characteristic. This is because a steeper SS significantly enhances the ratio of on-current to off-current at the turn-on voltage. Such an improvement in the current ratio directly translates to increased energy efficiency in the FET operation.

The sub-threshold slope essentially measures the change in gate voltage required to increase the drain current by a factor of ten in the sub-threshold (off-state) region. A steeper slope implies that a smaller change in gate voltage is needed to switch the transistor from off to on state. This feature is particularly valuable in applications where power efficiency is critical, as it reduces the power consumed during the switching process.

Prospects for quantum dot based FETs

Microelectronic devices of the present day primarily utilize crystalline inorganic semiconductors, such as silicon, which boast intrinsic mobilities capable of reaching up to 1000 cm² V⁻¹ s⁻¹. This high mobility is attributed to band-like transport rather than carrier hopping, and silicon-based devices can maintain operational lifetimes exceeding 50 years. For at least half a century, this has remained an unchallenged truth despite numerous efforts in exploring other material technologies.

Colloidal semiconductor quantum dots (QDs), with their size-tunable bandgap, low exciton binding energy, and high photoluminescence (PL) quantum yields, present a significant potential for application in electronic and optoelectronic devices. These QDs are processed inexpensively through solution methods, offering versatility unmatched by traditional crystalline inorganic semiconductors. Techniques like spin coating and the use of flexible plastic substrates, which are detached from the constraints of epitaxial growth on crystalline substrates, contribute to this versatility. However, despite these advantages, QD-based FETs have primarily served as research tools, supporting studies in carrier mobility and backing devices such as QD-based solar cells, rather than as standalone electronic devices.

The traditional surface capping ligands, crucial for regulating QD size and polydispersity during growth, and preventing aggregation in solutions, paradoxically form an insulating layer around QDs. This layer impedes efficient charge transport within a QD solid, presenting an inherent contradiction between strong quantum confinement and electronic charge carrier transport. Recent advancements have seen QD FET carrier mobilities increase, and the overall quality of QD films improve. As a result, several research groups have begun to report conduction mechanisms akin to band-like conduction observed in conventional bulk semiconductors, such as silicon. Yet, as pointed out by Guyot-Sionnest, the experimentally observed negative temperature coefficient of mobility below a certain temperature may not indicate the onset of band-like hopping but could align with a carrier hopping model. This is due to factors like size polydispersity, which create a level of disorder with an energy scale surpassing the coupling energy between dots, thereby impeding band-like conduction. Liu’s hypothesis suggests that limited disorder might allow the formation of finite domains within which minibands form, but interdomain communication of charge remains dominated by hopping.

The ongoing debate and improvements in carrier mobilities are a positive sign for the future of QD FETs. With the mobility threshold of 30 cm² V⁻¹ s⁻¹ surpassed in 2012, the focus has shifted to optimizing other parameters such as reducing hysteresis, lowering threshold voltages, and minimizing the bias stress effect. These efforts aim to realize the full potential of solution-processed colloidal QD FETs. Guidance for achieving these goals may come from research on organic FETs, such as in the selection of gate materials, and controlling the doping process will be crucial in developing low-cost p–n junctions and bipolar transistors.

Regarding commercialization prospects, while QD FET technology may not yet be ready to directly compete with conventional silicon CMOS in high mobility applications, it holds promise in specific performance areas. The processability of QDs, coupled with the potential for low-cost fabrication and the absence of a need for an epitaxial substrate, is beginning to attract commercial interest. Kim’s demonstration of flexible QD FET circuitry exemplifies how QD FETs might initially thrive as a niche technology, offering low-cost, low-power, flexible devices. Additionally, as noted by Guyot-Sionnest, QD films used in FETs have already surpassed mobilities suitable for low current applications such as photodetectors or photovoltaic cells.

Continued development of QD FETs will likely progress alongside efforts to refine colloidal QD films for other devices, like solar cells and sensors. For instance, Koppens and colleagues recently demonstrated high sensitivity in a photodetector by combining the optical properties of QDs with the transport properties of graphene. Given the significant advancements in colloidal QDs for electronic and optoelectronic applications in recent years, it is anticipated that colloidal QD FETs will transition from research driven by scientific curiosity to economically viable commercial applications in the foreseeable future.

Application of quantum dot transistor

Quantum-Dot Single-Electron Transistors as Thermoelectric Quantum Detectors at Terahertz Frequencies

Quantum Dot Infrared Photodetectors (QDIPs) are emerging as promising contenders for terahertz communication applications. When configured in a single-electron transistor (SET) geometry, these devices can achieve an exceptionally low noise equivalent power (NEP) of approximately 10−19 WHz−1/2 under precise bias control. Interestingly, even when the incoming radiation energy does not resonate with the intersubband transition of the QD, these devices maintain commendable detection capabilities, such as responsivities up to 100 A/W, largely due to the strong nonlinearity in their current-voltage characteristics.

In this context, QD millimeter-wave nanodetectors utilizing InAs/InAsP quantum dot (QD) nanowires (NWs) have been conceptualized and developed. These NWs, characterized by a small effective mass and favorable Fermi level pinning, lead to localized QDs with significant charging energy. By employing a double-barrier heterostructure for confinement, a QD SET is engineered. Upon irradiation, this device generates an additional electromotive force driven by the photothermoelectric (PTE) effect, which can efficiently detect incoming radiation with NEP levels as low as 8 pWHz−1/2. A key advantage of these PTE quantum detectors is their operation under zero bias, significantly reducing the dark current compared to traditionally biased systems.

Heterostructured semiconductor NWs have been recognized as a promising platform for creating sensitive, high-speed, and low-noise detectors across the terahertz spectrum. NW field-effect transistors (FETs) with controlled compositions are not only compatible with on-chip technologies but also exhibit attofarad-order capacitance, making them ideal for low-capacitance integrated circuits. While axially heterostructured NWs allow for tailored tunnel barrier properties, their capacity for a widely tunable tunnel coupling is somewhat limited compared to electrostatically defined structures. This characteristic is advantageous for applications like efficient thermoelectric conversion or single-photon QD detectors, which require varying tunneling rates. However, optimizing charge stability and tunneling is more effectively achieved by electrostatically engineering and tuning the orbital configuration within the QD.

The InAs/InAs0.3P0.7 QD–NWs employed in this research were grown via gold-assisted chemical beam epitaxy (CBE). This method facilitates the combination of semiconductors with different lattice parameters in axial heterostructures, aided by efficient strain relaxation along the NW sidewalls. The InAs/InP system is particularly suitable for creating high-quality axial NW heterostructures, such as QDs and superlattices, in Au-assisted growth. The low solubility of As and P in Au allows for atomically sharp interfaces in both growth directions. However, the growth of InAs/InP segments can be hindered by nucleation delays during the InP segment growth, affecting the growth dynamics. In contrast, growing InAs(1–x)Px alloys on top of InAs NWs avoids nucleation delays, leading to uniform growth and symmetric thicknesses for the same growth periods. The height of the tunneling barriers can be adjusted by modifying the P/As ratio in the alloy segments.

The InAs/InAs0.3P0.7 QD–NWs, confined by thin InAs0.3P0.7 barriers, exhibit quantum confinement along the NW axial direction. These NWs are integrated into planar laterally gated FETs, using a combination of electron beam lithography (EBL) and thermal evaporation. In this setup, the nanosystem functions as a few-electron transistor, and its electrical transport can be described within the constant interaction model framework. The self-capacitance of the QD (CΣ​) determines the charging energy (δ=e2/CΣ) needed to add one electron to the dot. The capacitance between the QD and the gate electrode defines the gate lever arm (αG=Cgd/CΣ), relating to the capacitive coupling with the gate electrode. If δ≥kBT, where kB is the Boltzmann constant and T is the temperature, the source to drain current exhibits sharp peaks as a function of the gate voltage (VG), corresponding to the resonant tunneling of single electrons through the QD and reflecting Coulomb interactions between electrons. In the Coulomb blockade regime, the voltage interval between consecutive peaks is defined by the sum of the energy level spacing (ΔE) and the charging energy. By selecting appropriate geometrical parameters for the dot, such as NW radius (Rnw) and width of the InAs segment between the two InAs0.3P0.7 barriers (Wqd), the distance between consecutive energy levels can be tailored to resonate with a desired photon energy.

Figure 5: (a) Scanning electron microscopy (SEM) image of a planar on-chip split bow-tie antenna. One side of the antenna is connected to the source electrode, while the opposite side is connected to the arms of double lateral gate contacts. (b) SEM image of a prototypical quantum-dot nanowire (QD–NW) single-electron transistor (SET). (c) SEM image of a forest of epitaxially grown InAs nanowires. (Inset) Scanning transmission electron microscopy (STEM) image of a single InAs/InAsP QD–NW. (d) Color map of the gate–QD capacitance (Cgd) as a function of the QD axial dimension (distance between the barriers, Wqd) and NW radius (Rnw), calculated numerically using an electrostatic simulation of the QD–NW FET performed with commercial software (COMSOL Multiphysics). (Inset) Three-dimensional image of the SET channel overlaid to the simulated distribution of electrostatic potential around the InAs QD. The simulated Cgd value is 1.1 aF for our specific device geometry (Wqd = 18 nm and Rnw = 25 nm). Credit:

The temporal response of the proposed quantum dot (QD)–nanowire (NW) photothermoelectric (PTE) device is evaluated through an analysis of its transport characteristics. Experimentally, it is demonstrated that the time scales governing the dynamics of heating and cooling carrier density in InAs NWs range between 40 femtoseconds (fs) and 4 picoseconds (ps). These time scales are notably swifter than the detector’s rise and fall times, which are confined by the electrical time constant τRC=RtCt. This constant is estimated to be in the range of approximately 1 to 10 nanoseconds (ns), with Rt (ranging from 1 to 10 MΩ) representing the photodetector resistance and Ct (about 1 fF, inclusive of the bow-tie shunt capacitance simulated using COMSOL Multiphysics’ electrostatic module) representing the capacitance.

The impressive performance of the QD–NW platform, coupled with its extraordinary adaptability in terms of geometry and chemical composition, and the inherently broadband and zero-bias nature of the PTE detection mechanism, sets the stage for significant enhancements in the quantum detection concept. For instance, an optimization strategy for PTE conversion might involve reducing the tunnel coupling between the dot and the leads, engineering the energy level spacing, and leveraging quantum phenomena such as the Kondo effect. This approach aims to strike a balance between detector sensitivity and speed.

The findings from this study pave the way for integrating terahertz technology with few-electron physics to tackle some of the foremost challenges in quantum science. This includes areas like quantum key distribution, quantum communications, and quantum sensing, where sub-shot noise NEPs along with high quantum efficiencies are pivotal. Moreover, the research provides a comprehensive understanding of the broadband PTE-driven photoresponse within a QD–NW structure. It establishes a framework for distinguishing the various physical phenomena that transpire when the energy of the impinging photon corresponds to the QD level spacing.

The adaptability offered by quantum engineering, to optimize both transport and optical properties of the device while aligning the photon energy with the QD energy levels, renders the InAs/InAsP heterostructured NWs an exemplary component in quantum optics and nanophotonic applications. These applications necessitate precise control over individual photon paths, highlighting the crucial role of these heterostructures in advancing quantum technology.

Recent research for Quantum dot transistor

Recent advancements in quantum dot transistors are highlighted by the development of single PbS (lead sulfide) colloidal quantum dot transistors. These are made from tiny semiconductors, smaller than 10 nanometers, and are processed in a liquid form. This represents a major breakthrough because these transistors can work as single-electron transistors (SETs) at high temperatures, something that was hard to achieve before.

The ability of these quantum dot transistors to operate at high temperatures is a big deal. It overcomes a long-standing challenge in making devices that can work stably at such temperatures. This progress opens up new opportunities for using and studying advanced electronics. It highlights the potential of PbS colloidal quantum dots to improve how transistors work and increase their performance. This sets the stage for more durable and versatile electronic devices in the future.

Schematic illustration of the device structure and the experimental setup
Figure 6: a Schematic illustration of the device structure and the experimental setup. b Scanning electron microscopy image of 10-nm-thick Au electrodes separated by a ~ 5 nm gap onto which PbS CQDs (diameter d ~ 3.6 nm) have been deposited. c Current–voltage (ISD–VSD) curves measured for sample A at T = 4 K, taken at every 1 V step of the back-gate voltage, VG, from 0 V to 30 V. The curves are offset by 0.02 nA for clarity. Only the bottom curve at VG = 0 V corresponds to the actual scale.. Credit:

Colloidal quantum dots (CQDs) are tiny semiconductor crystals known for their excellent light emission and absorption properties. Their optical bandgaps can be finely adjusted, making them ideal for high-temperature single-electron transistor (SET) operations. This is a big deal for quantum information devices because it means better control over electricity and easier reading of quantum states in each CQD. Such advancements could lead to major progress in quantum information technology, especially by combining optical and electrical ways to manipulate quantum states.

CQDs are also great for making thin films and moving carriers when they are linked together. This makes them key candidates for cutting-edge optoelectronic devices like solar cells, photodetectors, and light-emitting devices. Among CQDs, PbS (lead sulfide) CQDs are particularly notable for their wide emission and absorption in the infrared range, which is crucial for studying how charge carriers move.

A recent study featured single-CQD transistors made from high-quality PbS CQDs using oleic acid as a ligand. These transistors have several unique characteristics: the quantum dot size affects carrier transport, the electron charging energy and conductance depend on the orbitals, and an applied electric field can change the electron confinement potential. Interestingly, these devices showed the Kondo effect, which is related to coherent carrier transport influenced by spin. It was also found that smaller CQD transistors could work as SETs even at room temperature, highlighting their potential in quantum information and optoelectronic devices.

Transport measurement studies revealed that the current between the source and drain in these transistors is affected by the back-gate voltage, a phenomenon called the Coulomb blockade effect. The Coulomb stability diagrams from these transistors show that electron transport heavily depends on the quantum dot size, with different behaviors in small and large CQDs.

Further analysis showed that the electron wavefunction in PbS CQDs grows with more electrons, affecting tunneling conductance. The Kondo effect in these systems was also examined, showing that spin-dependent carrier transport in single PbS CQDs creates a spin singlet state. This state occurs between unpaired electrons in the CQD and opposite-spin electrons in the electrodes, and is particularly seen in odd-numbered Coulomb diamonds. This suggests a strong connection between the electrodes and CQDs, even with the insulating oleic acid ligand present.

Challenges and Limitations of quantum dot transistors

Challenges and Limitations of quantum dot transistors

Quantum dot transistors are part of a growing field in electronics. Quantum dots are really small crystals that can carry electrons because of their unique quantum properties. They also glow brightly, which is useful for many electronic applications. But it’s not easy to use these tiny dots in practical, high-performing devices.

One big challenge is to mix n-type and p-type devices in the same layer of quantum dots. This mix is important for creating special kinds of circuits, called CMOS logic, which are needed for fast, energy-efficient devices.

There’s some progress, though. For example, using a material called copper indium selenide in quantum dots looks promising. It’s safer and easier to use for making both n-type and p-type devices together.

Making quantum dots is tricky too. They’re created with chemical methods that need very careful control over the ingredients, timing, and temperature. The dots need to be uniform in size for good quality, and their surface affects how they work electronically. Adding certain molecules to the surface can make them work better, but it’s a delicate balance to keep them stable and working well.

As we make these devices smaller, down to nanometer sizes, new problems show up. Tiny effects, like tunneling, start to use more power, make more heat, and can cause errors. Making such small devices is also complex and expensive.

Quantum dot transistors could be great for flexible electronics, like bendable gadgets. They’re made with methods that could be useful for things like consumer electronics and medical devices because they’re safe and fit well on flexible materials.

To really make the most of these tiny transistors, we need to solve these challenges in making and using them. There’s a lot of potential, but more research is needed for them to be used widely.

Electronics and Telecommunications engineer with Electro-energetics Master degree graduation. Lightning designer experienced engineer. Currently working in IT industry.