EducationWhat is Unipolar / Field-Effect Transistor? - Basics and Definition

What is Unipolar / Field-Effect Transistor? – Basics and Definition

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Unipolar / FET Transistor Basics

FET basics

Field-Effect Transistor (FET) – Also known as Unipolar Transistor, is a three-ended (three electrodes), voltage-controlled semiconductor electronic component that has the ability to amplify the electrical signal. FET family consists of a group of several types of different components, whose common feature is the indirect effect of the electric field on the semiconductor resistance or the resistance of the thin, non-conductive layer. Theoretically, the field effect transistor can be controlled without power consumption. Only one type of load carriers takes part in the operation of the component, hence the unipolar name, while the control of output current is done with the use of electric field (field effect transistors).

FET – Internal construction and principle of operation

Unipolar Transistor has three electrodes:

  • Drain “D” – the electrode where the load carriers reach. Drain current – ID, drain-source voltage – VDS,
  • Gate “G” – the electrode controlling the flow of charges. Gate current – IG, gate-source voltage – VGS,
  • Source “S” – the electrode from which the load carriers flow to the channel. The source current is denoted as IS.

These are equivalents to the electrodes in bipolar transistors. Two of them: Drain and Source are connected to the properly doped semiconductor crystal. Between these ends, the channel is created through which the current flows. The third end is placed along the channel: Gate, thanks to which we can control the flow of the current. In case of connecting multiple MOS transistors in an integrated circuit, the fourth electrode is often used: B – Body (or Bulk) in order to bias the substrate. But in general this end is connected with/to the source.

FET – Tasks for students

If you are a student or simply want to learn how to solve Field-Effect Transistor tasks, please visit this section of our website where you can find a wide variety of electronic tasks.

Division of FETs

Depending on the operation principles and laws, we can distinguish two main types of FETs, whose are further divided as shown on the Fig.1. below:

types of fet
Fig. 1. Division of field effect transistors

JFET – Construction and operation principle

The JFET transistor consists of an n-type semiconductor layer in N-channel JFET transistors or p-type semiconductor in P-channel JFET transistors. These layers form a channel. Electrodes are connected to both ends of the channel. In the JFET transistors, the gate is insulated from the channel by the reverse-biased junction (with very high input resistance).

JFET transistors should be polarized in a way, that the carriers move from the source to the drain and the gate-channel junction should be reverse-biased.

There aretwo variants of this junction:

  • P-N junction (PNFET),
  • M-S junction (Metal-Semiconductor).

The channel through which the current will flow is located between the drain and source. One can control the width of the channel (its resistance) by changing the gate-source voltage (VGS). Increasing VGS voltage (which reverse-bias the junction) causes narrowing of the channel until its completely “closed” – the current won’t flow. To the VGS voltage, the voltage drop between a specific point of the channel and the source (VDS) is added. Increasing the value of VDS voltage will ultimately connect depletion layers and block the channel by saturating the transistor. The value of Drain current ID won’t rise regardless of further increasing the VDS voltage, and transistor becomes a very good transconductance component.

  • P-N JFET (normally on)
Jfet symbols
Fig. 2. JFET symbols
construction and working of jfet
Fig. 3. Inner structure of JFET with “N” channel type

MOSFET (Metal-Oxide Semiconductor FET) – Construction and operation principle

In MOSFET transistor, the gate is insulated from the channel with the dielectric layer. The area marked “N+” is heavily doped “N” type semiconductor. In case of E MOS transistors with a voltage of VGS = 0, the channel is blocked (its resistance takes the value of MΩ and the ID current doesn’t flow). By increasing the VGS voltage channel increases its conductivity and after reaching a certain value called VT threshold voltage, the flow of the ID drain current was possible through the channel. MOSFET’s drain current is regulated by the gate’s voltage signal of the value up to several volts, which ensures compatibility with every MOS systems, especially CMOS. The power needed to control it is very small, and the safe operation area is larger compared to BJT transistors. In addition, switching times are also shorter compated to BJTs.

The minimum resistance value of the channel specified by the manufacturer can be found in datasheets as rdson (it’s dependent on the maximum voltage of the VDS transistor. The value of ID current that will flow through the created channel is dependent on the VDS voltage, but it isn’t a linear relation. It’s described by the formula:

βcurrent amplifier ratio
This current affects on the gate bias state by changing it, which results in a narrowing of the channel near the drain. In case of further increasing the gate-source VGS voltage, the cut-off of VGSoff voltage will be exceeded at some point causing the loss of created channel (VGS= VDS)

  • Depletion mode MOSFET – D MOS (normally on):
Mosfet symbols
Fig. 4. D MOS symbols
  • Enhancement mode MOSFET – E MOS (normally off):
Mosfet symbols
Fig. 5. E MOS symbols
Mosfet structure
Fig. 6. Inner structure of E MOS with “N” type channel

FET – Operating modes

There are three operating modes of the transistors:

  • Cut-off mode: |VGS| > |VT| at any |VDS|,
  • Active mode (also known as linear or unsaturated): |VGS| < |VT| and |VDS| <= |VDSsat|,
  • Saturation mode: |VGS| < |VT| and |VDS| => |VDSsat|.

Note: In many countries Voltage unit and symbol is called “V” instead of “U”, like in this article.

FET – Basic parameters

  • VDSmax – the maximum drain-source voltage,
  • IDmax– the maximum drain current,
  • VGSmax– the maximum gate-source current,
  • Ptotmax– permissible power loss,
  • VT– the threshold voltage at which current begins to flow,
  • IDSS(VGS=0) – the saturation current at determined VDS current,
  • gm [S-Siemens] – transconductance ratio,
  • rds(on)– the minimum resistance value of the channel of the transistor operating in the unsaturation mode,
  • IGmax– the maximum allowable gate current,
  • ID(OFF)– the drain current in cut-off mode – at a voltage |VGS| > |VGS(OFF)|.

FET – Current-voltage characteristics

Transfer characteristics – they describe the relation of ID drain current from the gate-source VGS voltage with determined drain-source VGS voltage.

  • JFET “N”:
FET characteristics
Fig. 7. JFET “N”
  • D MOS “N”:
Mosfet characteristic
Fig. 8. D MOS “N”
  • E MOS “N”:
Mosfet characteristics
Fig. 9. E MOS “N”
  • Drain characteristics (for “N” type FET) – it describes the relation of drain Icurrent from the drain-source VDS voltage with determined gate-source VGS voltage. The characteristics area was divided into two parts: the active and saturated scope.
Unipolar characteristics
Fig. 10. Drain characteristics (for “N” type unipolar transistor)

Practical application – Unipolar MOSFET – NMOS transistor

In the practical exercise, the effect of the NMOS transistor in its simplest form is shown as a transistor key. Such use mainly operates in microcontroller applications, it is used to control the signal from the microcontroller to external receivers.

For this exercise we will need the following things:

The circuit connection schematic looks like this:

Fig. 11. Circuit connection schematic: V2: 9V DC power supply, D1: White LED, R1: 220 ohm resistor, M1: BUZ11 transistor, R2: 1k ohm resistor, V1: 3V battery (in the schematic sinusoidal source is used to illustrate transistor operation). Please note, that symbols on the schematic are different for the transistor but have similar parameters as BUZ11.

The finished connected circuit on the breadboard is shown below on the Fig. 12:

Fig. 12. Illustration of the breadboard connection

System after connecting the 9V power did not show any action. After connecting the battery to the circuit, the LED started to glow. This is the simplest way to illustrate the principle of the operation of voltage V(breakdown voltage) in unipolar transistors. In the BUZ11 transistor, the voltage VGSTh range is from 2.1 to 4 V. With the use of 3V batteries, we obtain the sufficient voltage to open the channel between the drain and the source in the unipolar transistor. After that the LED starts to glow.

Fig. 13. One more illustration of the breadboard connection and operation

In addition, on the waveform below we can see the voltages on the V(n005) battery, which varies between 3 and -3V and are applied to the gate of the transistor, between the current on the LED I(D1). Additionally, on the waveform we can see the VDS voltage, the appearance of the waveform depends on the time of switching on the transistor.

Fig. 14. Illustration of the breadboard connection
Michal Pukala
Electronics and Telecommunications engineer with Electro-energetics Master degree graduation. Lightning designer experienced engineer. Currently working in IT industry.



  1. Thank you.
    There’s so much confusing resources about *FET that finding your page has been a gift from Google.
    As a non-formally trained person it’s hard to get to understand all of this as resources are scarce.
    I’d suggest you also add the info about Ugs being equivalent to Vgs (U == V) since it seems to change based on conventions.

    keep it up 🙂
    ubi de feo