SPI communication – How SPI works ?

The SPI communication interface belongs to the full duplex interfaces, which means sending and receiving a signal at the same time. The SPI interface belongs to the family of synchronous interfaces, i.e. clock signal transmission, which allows synchronization of any system connected to the interface. The MASTER system is responsible for generating the SPI clock signal and starting the transmission of the signal. Other circuits connected to the same SPI interface take the form of SLAVE.

SPI standard

The construction of the SPI bus consists of four communication lines.

– MISO is Master in Slave out, means the line that connects the slave output to the master input,

– MOSI is Master out Slave in, a line that connects the master output with the slave input,

– SCK is a serial clock, a zero signal, it is designed to synchronize circuits,

– CS is chip select, a line informing slaves about the start of transmission, activation of slaves is performed using a high state, and deactivation by means of a low state, the signal is negated.

SPI principle of operation

The SPI interface is built on shift registers, which consist of type D flip-flops. The synchronization of each of them is performed by means of a clock signal. There are 8 flip-flops with numbers from 0 to 7. A logic state is entered at the input of flip-flop No. 0, which starts the transmission frame.

Each flip-flop stores one byte of data. The MASTER system generates a zero signal using a generator. The combined MOSI and MISO lines form a closed ring, thanks to which the data transfer is continuous but not constant, every eight clock cycles of the generator are sent the entire byte of data. The register value can be changed every 8 clock cycles.

SPI communication type

To read data from the SLAVE system, the system must send only zeros at the same time informing about its presence MASTER. There is a three-state buffer at the SLAVE output. When SLAVE is switched off by MASTER, the three-state buffer disconnects the shift register from the entire bus, thanks to which the SLAVE system cannot be seen through MASTER.

A typical type of SPI interface connection is a bus line connection. In this setting, MOSI, MISO and SCK lines are connected in parallel. Connection of the CS line is separate for each SLAVE. This is done in such a way as to activate each system individually.

SPI data frame

Sending data frame for SPI interface isn’t set by default. As bus users, we can determine whether frame sending will start from the oldest bit or the youngest bit. Data shifting in registers can also be set for the falling or rising edge of the SCK signal.

SPI Clock Polarity and SPI Clock Phase

The SPI idle state must match on the connected master and slave device. Additionally, the data clocking method during the transfer through the SPI interface must be the same.

Clock Polarity CPOL is an indicator that allows you to determine the level of the clock signal for the idle state.

CPOL 0 – Low status for idle state

CPOL 1 – High status for idle state

CPHA or the clock phase parameter determines the moment of sampling and presenting the data.

CPHA 0 – The first edge is responsible for sampling the signal of the first bit for the SCK line. The second edge is for the presentation function. The starting data bit must be prepared before transferring the first edge of the SCK line.

CPHA 1 – The first edge for the SCK line is used for data presentation. The second edge, on the other hand, is responsible for signal sampling.

The following schematic drawings show combinations for clock polarity settings and for clock phases.

Advantages and disadvantages of the SPI interface

Adventages:

• Full-duplex communication type
• Much faster data transfer compared to I2C interfaces
• Freedom to define the type of data transmission protocol (no restrictions for the maximum value of 8-bit, no addressing required)
• Very simple structure of spi hardware (emulation thanks to bit-banging, SLAVE connection allows for synchronization of transmission for SCLK signals)
• Parallel transmission requires few connections for spi hardware

Disadvantages:

• More occupied pins than in the I2C interfaces
• It has no hardware control for data flow
• No control bits between MASTER SLAVE devices
• The spi hardware system can have only one MASTER device
• Small maximum distance for data transmission

3 wire SPI connection example DS1868 with SPI microcontroller PIC16F872

An example component in this configuration is DS1868. It is a dual digital potentiometer connected via the 3 wire spi interface. The device that will manage the operation of the potentiometer is spi microcontroller with an active SPITM interface.

Normal SPI interface and 3 wire spi interface differ in signal types, but they are compatible. As for the 3 wire interface, the signals are DQ – signal with input data, Cout – main data, RST – switching signal, Active-Low – switching signal, CLK – clock signal.

Data storage from the DS1868 potentiometer

Connecting the spi microcontroller to the DS1868 requires the MSB to be sent first. When writing data, the data frame contains 7 bits for the first byte which are pushed out of the shift register. The LSB for the first byte is in b0. The transfer data frame is 3 bytes long. This includes 17 data bits and 7 addressing and initialization bits.

Reading data from DS1868

The transmit data frame for the DS1868 in 3 wire spi transmission looks as below in the figure. First, the stack select bit called b0 is sent, followed by the MSB of data from potentiometer # 1, then data from the next potentiometer. There are an additional 7 bits in the third data byte.

The flowchart for saving and reading data is presented below. The stack select bit is accommodated by byte 1, which is 0Fh. Byte 0 of the data frame has a value of 55h. The bytes to be written to the DS1868 device are those with the values 01h, 0Fh, 55h. The additional 7 bits are contained in the leading zeros 01h of the address. The SPI microcontroller first sends the MSB value, i.e. 01h. The leading zeros drop off and the value 1 ends at b0. In the first data frame, the first 4 bits are 0, the last 4 bits are filled with 1. The remaining bits change between 0 and 1. The value of the MSB bit in the pool for 0 is also 0.

• Byte 0: 00000001b (01h)
• Byte 1: 00001111b (0Fh)
• Byte 2: 01010101b (55h)

The 3 byte output values have the following values, and b0 is the first bit for reading.

• Byte 0: 10000111 (87h)
• Byte 1: 10101010 (AAh)
• Byte 2: 10,000,000 (80h)

The 7 additional bits are now at the end of byte 2.

The TRISx register establishes the pins to either input (1) or output (0 ). The PORTA register will certainly regulate the energetic reduced RST and the LED to 5V or 0V.

TRISA =– 1xxx00 – RA5 active-low SS is readied to input. It is used to make it possible for the serial port. RA0 and RA1 are readied to outputs for energetic low signal RST and also LED diode.

TRISB = lack of usage

TRISC = xx010xxx – Cleaning SCK i SDO, set SDI

The active-low RST pin should be set before sending out/ obtaining information and then must be removed after the sending data frame.

SPI settings

SSPSTAT = 01000000 (40h) – SMP bit = 0, CKE little bit = 1

When SMP = 0, the input data is tested at the end of the data exit time.

When CKE = 1, transmission occurs at the shift from the active clock state to the idle state when CKP = 0.

The SSPSTAT register establishes the clock and information to have the appropriate timing to link to the DS1868.

SSPCON = 00100001 (21h) – bit SSPEN = 1, bit SSPM3-0 = 0001

SSPEN = 1 enables the serial port.

SSPM3-0 has picked the clock regularity. SSPM3-0 = 0001 = Fosc/ 16 = 20 MHz/ 16 = 1.25 MHz

DS1868 has an optimum clock frequency of 10 MHz.