SPI communication – How SPI works ?

The SPI communication interface belongs to the full duplex interfaces, which means sending and receiving a signal at the same time. The SPI interface belongs to the family of synchronous interfaces, i.e. clock signal transmission, which allows synchronization of any system connected to the interface. The MASTER system is responsible for generating the SPI clock signal and starting the transmission of the signal. Other circuits connected to the same SPI interface take the form of SLAVE.

SPI standard

The construction of the SPI bus consists of four communication lines.

– MISO is Master in Slave out, means the line that connects the slave output to the master input,

– MOSI is Master out Slave in, a line that connects the master output with the slave input,

– SCK is a serial clock, a zero signal, it is designed to synchronize circuits,

– CS is chip select, a line informing slaves about the start of transmission, activation of slaves is performed using a high state, and deactivation by means of a low state, the signal is negated.

SPI principle of operation

The SPI interface is built on shift registers, which consist of type D flip-flops. The synchronization of each of them is performed by means of a clock signal. There are 8 flip-flops with numbers from 0 to 7. A logic state is entered at the input of flip-flop No. 0, which starts the transmission frame.

Each flip-flop stores one byte of data. The MASTER system generates a zero signal using a generator. The combined MOSI and MISO lines form a closed ring, thanks to which the data transfer is continuous but not constant, every eight clock cycles of the generator are sent the entire byte of data. The register value can be changed every 8 clock cycles.

spi construction

SPI principle of operation

SPI communication type

To read data from the SLAVE system, the system must send only zeros at the same time informing about its presence MASTER. There is a three-state buffer at the SLAVE output. When SLAVE is switched off by MASTER, the three-state buffer disconnects the shift register from the entire bus, thanks to which the SLAVE system cannot be seen through MASTER.

A typical type of SPI interface connection is a bus line connection. In this setting, MOSI, MISO and SCK lines are connected in parallel. Connection of the CS line is separate for each SLAVE. This is done in such a way as to activate each system individually.

spi communication

SPI parallel communication

SPI data frame

Sending data frame for SPI interface isn’t set by default. As bus users, we can determine whether frame sending will start from the oldest bit or the youngest bit. Data shifting in registers can also be set for the falling or rising edge of the SCK signal.

spi data frame

SPI data frame

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