How does a not gate work
From the previous articles we discussed about Logic gates. Today we are going to dig deeper in NOT gate. NOT gate is the most basic gate among the logic gates we discussed from the previous article. NOT gate consists of only one input and generates inverting(complementing) voltage signals corresponding to binary conditions True(high) to False(low) and False(low) to True(high) which can be also represented by o’s(false) and 1’s(true). The NOT gate does not amplify the signals and it is mostly seen in integrated circuits (ICs). This gate is also known as Inverting Buffer or Inverting gate.
The “O” mark which is at the end of the Traditional and IEC symbol of the gate denotes the complementation of the input signal. This is also called as the Bubble symbol, and this can also placed at the beginning of the diagram to indicate an active – LOW input. This symbol is not limited to the NOT gate, we can apply these for any other digital circuits, and it represents the negation of the corresponding signal.
Not gate truth table
Following is the truth table for NOT gate. Let’s label A as input and the Q is the output.
Transistor not gate
We can design a simple NOT gate inverter circuit using a single stage transistor switching circuit as shown in the diagram below. When the base of the transistor circuit is HIGH, the transistor starts to conduct and the current in the collector starts to flow. This produces a voltage drop across the Resistor connected to the collector and connects the output point at “Q” to ground making a zero-voltage output at point “Q”. When the base of the transistor is LOW, the transistor starts to stop the current flowing through the resistor connected to the collector. This produces a output voltage of HIGH at point “Q”. Then if the input voltage at the point A is HIGH the output voltage at the point Q will be LOW.
We can easily design and build a NOT gate using a single N-type Metal Oxide Semiconductor transistor using a P-type Metal Oxide Semiconductor transistor by coupling it with a resistor. This can be fabricated at lower manufacturing costs compared to others.
There are methods to design NOT gate inverters using two inverting transistors which uses Complementary Metal Oxide Semiconductor configuration. Though this design manufacturing costs are higher than the others it consumes less power and has a high processing speed.
We can easily design and build a NOT gate using Bipolar Junction Transistors. The design is based on the class of digital circuit build which is also known as resistor transistor logic. It is built using resistors considering them as the input network. We can develop a simple two input circuit as shown in the diagram below. The bipolar junction transistor must be saturated “HIGH” (“ON”) for a complemented output “LOW” (“OFF”).
Usually digital electronic circuits operate in constant levels of 5V, 3V for “HIGH” state and 0V for LOW state. These states HIGH and LOW corresponds to logical 1 or 0 respectively.
NOT gate circuit
Practical Inverter NOT circuit
The circuit of a practical inverter NOT circuit is made up of diodes, resistors and bipolar junction transistors. This works same as the other inverter circuits designs it inverts the given input signal.
Schmitt Inverter
A Schmitt trigger is a circuit which generates an output waveform of a square wave of a particular duty cycle. It can be implemented on several devices, however most commonly on the operational amplifier.
This helps to avoid the errors that is related to the noise in the input signals. The Schmitt inverter is developed to operate within certain boundaries. If the input signal goes beyond the Upper Threshold Limit the output changes to “LOW” and the signal goes below the Lower Threshold Limit output changes to ‘HIGH”. This inverter has some form of Hysteresis that is built into its switching circuit.
Schmitt NOT Gate Inverter Oscillator
The diagram in the left side shows a simple Schmitt inverter to generate a square wave output waveform. At the beginning the capacitor is discharged completely, therefore the input of the inverter in “LOW” which gives and complementary output “HIGH”. Capacitor starts to charge when the output is sent back to the input of the inverter.
There is an upper voltage threshold and lower voltage threshold limit for the above inverter. When it reaches threshold limits state of the inverter changes. In the upper limit the state changes to “LOW”. After that it gets to the lower threshold limit and inverter changes its state again(“HIGH”). This change causes a square wave output with a 0.33 duty cycle.
The diagram in the right side also produces a square wave output but with a sinusoidal input. The input of the circuit is connected to a capacitor which is connected to a potential divider. This capacitor will reduce the DC noise in the input signal. This inverter also has upper and lower threshold limits as the previous one and act as the same.
7404 NOT Gate
7404 NOT gate is Integrated Circuit which has six inverters build inside. All of the six inverters act as logical NOT gates which gives inverting output as the input signal. (when the input is “HIGH” the output is “LOW”).
Hex Schmitt Inverters
The logic functions are the same as the other inverters. In here we have 6 independents NOT gates which can invert six digital signals, simultaneously. Various families will have various logic levels and various delays. Regular logic gates assume the speed of the signal is very fast from one state to the other. In certain voltage levels the gates will act as linear amplifiers, unless they are Schmitt gates. There are various uses of the Hex Schmitt inverter. They are reducing the noise in the signal, adding small delays to the original signal, shifting the levels, converting between logic families, relaxation oscillator etc.
Transistor-to-Transistor Logic (TTL)
Transistor to Transistor Logic is digital circuit design acts on direct current pulses and based on BJTs. These are built using Bipolar Junction Transistors and both the logic function and also the amplification is done by the transistor. Inverter is the most basic transistor to transistor logic circuit. It has an only one transistor with its collector connected to Vcc with pullup resistor and emitter connected to the ground. The output is taken from its collector. Transistor goes to saturation region when the input is “HIGH” (logic 1) and the output voltage will get “LOW” (logic 0).
Sourcing Currents
The direction of the direct current flow between Transistor- transistor logic gates is referred using the help of Current Sinking and Current Sourcing. Positive end is called as the sourcing end and the ground is called as the sinking end.
To complete the full circuit the Transistor to Transistor Logic gates should consist a voltage source and a ground reference. Both the input and the output can be either source direct current or a sink. When one gate feeds a signal to the other the both actions of sinking and sourcing occurs simultaneously occur in the Transistor to Transistor Logic gates.
Normally the sourcing output directly links to the sinking input. The load is driven by the current supplied from the source current. This current sourcing is done using a PNP transistor and it also makes space to provide positive potential.
Sinking Currents
The upper limit of the current which a pin can absorb over a load linked to an outside supply is denoted by the Sinking Current. Sinking delivers a path to minimum potential of zero or ground with the help of an NPN transistor.
Not Gate Applications
To build any sort of non-trivial digital device, we must have NOT gates, or inverters. Any digital circuit can be constructed of just NOT and AND gates (NAND gates), or NOT and OR gates (NOR gates).
But we cannot use just AND or OR gates by themselves, without NOT gates, because any non-trivial digital circuit will require the inversion of some signals and we can’t do that with just AND or OR gates.
So, every digital device that we have such as smart phone, tablet, personal computer, etc. has millions or billions of transistors acting as inverters or NOT gates.
