From the previous article, we discussed simple logic gates. In fact, we can use switch networks to build a gate that implements any Boolean function. CMOS is a type of MOSFET (metal-oxide-semiconductor field-effect transistor) which is used in digital circuits to perform logic functions. For the functions, it uses n-type MOSFETs and p-type MOSFETs. CMOS stands for complementary metal-oxide-semiconductor and it is mostly used in integrated circuits, microprocessors, microcontrollers, memory chips, and analog devices such as RF circuits and image sensors.
The key is to realize a CMOS gate is just two switch networks, one to Vdd and one to Gnd. Practically, the kinds of gates that you can construct are limited by the need for stacks of series transistors and their effect on gate performance. To better understand these issues, we next look at capacitance, where it comes from, and how it affects the performance of gates (provides memory, and delay).
To build a logic gate f (x1, …, xn), need to build two switch networks:
- The pullup network connects the output to Vdd when f is false
- The pulldown network connects the output to Gnd when f is true.
CMOS gate capacitance
CMOS are a type of MOSFETs; therefore, they have a gate capacitance that we take into account where it comes from, and how it affects the performance of gates. Gate is made of an oxide layer which separates the gate and channel. When a positive voltage is applied to the gate, the flow of electrons to the channel from the source begins. Then the electrons are collected near the channel until the gate voltage becomes greater than the threshold voltage. Then the electrons flow starts to travel from the source to the drain.
During the process of electrons moving the source to the drain, there is a capacitor in the middle of the channel and the gate. This capacitance is called gate to source capacitance and is measured using the following equation.
When we consider the practical implementation, we have to consider all the internal capacitances inside the MOSFETs. All of those capacitances depend on the gate-source voltage and the drain-source voltage. They are as follows: gate – gate-drain, drain-source, gate-substrate, and other capacitances.
CMOS gate array
The way that application-specific integrated circuit (ASIC) manufacturers design and produce a prefabricated chip with components that are then organized into logic devices which are customized according to the purposed is called a gate array. ULAs (Uncommitted Logic Arrays) and semi- customs chips are the other names for the gate arrays. CMOS gate arrays are completed by designing and stick to the top metal layers that offer the interconnecting ways to form logic gates such as NAND, NOR, XNOR, etc. There are new types of CMOS gate arrays in the market with having features with medium speed, wide operating voltages while ensuring a reliable CMOS process.
CMOS Gates
When a system is built according to the principle of pMOS pull-up network connected to the Vdd and nMOS pull-down network connected to the output /GND we call that system a complementary metal-oxide-semiconductor (CMOS) gate. Most of the CMOS logic gates are manufactured using insulated-gate field-effect transistor (IGFET / MOSFET) transistors. It is rare to see CMOS logic gates manufactured using bipolar junction transistors.
The nonlinearities of the field-effect transistors occur due to the transistors not operating in the active modes are neglected here in the CMOS gates. But there are some other challenges to CMOS. They are high sensitivity to the high voltages that are emitted by the electrostatic sources and the CMOS gates might get activated due to the left floating conditions.
CMOS floating Input
Due to the floating conditions, CMOS logic gates have to face problems. Such problems arise when the input to a CMOS logic gate is operated using a single throw switch when there are two states having inputs directly connected to the Vdd or ground pins and having inputs with floating or not connected to any other pins.
In the above diagram when the switch connected to the input is closed, the gate sees a definite input with a “LOW” or ‘0’ signal. But when the switch is in an open state the input logic level will uncertain due to the floating or not connected to any other pins.
The above problem is also raised when the input pin of a CMOS gate is connected to an open collector transistor-transistor logic gate. This happens due to the output of the transistor-transistor logic gate sometimes goes to a high state and the CMOS gate input will go to an uncertain floating state.
According to the above figure when the output of the transistor-transistor logic gate circuits goes to the “HIGH” state (“1” condition), the CMOS gate’s input will go to an uncertain state where the input will be floated to the left.
However, there are solutions to the above-described problems. One solution is connecting a pullup resistor in between the switch and the input of the CMOS gate and connecting the resistor to the Vdd. When we connect a pullup resistor, the resistor provides reduces the floating problem by providing a stable logic level for the state.
According to the above diagram when the switch is closed the CMOS gate will set to a definite low (‘0’) input and when the switch is open CMOS gets a reliable “HIGH” input with the help of the pullup resistor.
Another solution for this is using pulldown resistors. When we use pulldown resistors when the switch is closed, the gate will see a definite ‘HIGH’ or ‘1’ input and when the switch is open, the pulldown resistor will provide the connection to the ground needed to secure a reliable “LOW” or “0” logic level for the CMOS gate input. The diagram given below shows how we use the pulldown resistor to mitigate the problem of floating-point.
There is another solution to mitigate the floating-point problem when using multiple-input CMOS gates. It is using multiple pullup and pulldown resistors separately to the separate gate inputs as shown in the diagram below. This will use the same principle as the other two methods.
CMOS NAND Gate
CMOS NAND gate is shown in the diagram above. According to that, we can see that the Q1 and Q3 transistors are directly connected to Input A. When the input is “HIGH” or “1” the top transistor will be turned off and the bottom transistor is turned on. The opposite will happen when the input is “LOW” or “0”. The same procedure is gone through the Q2 and Q4 transistors. This will result in the output will be “HIGH” or “1” when the top transistor saturates, and the output will be “LOW” or “0” when only the two transistors at the bottom saturate.
CMOS AND gate
CMOS AND gate are designed by adding an inverter circuit to the CMOS NAND gate. This inverter circuit is usually added near to the output port of the CMOS NAND gate as shown in the diagram below.
CMOS NOR Gate
CMOS NOR gates also built using four MOSFETs, but the arrangement of the transistors in the CMOS NOR gates is different than the CMOS NAND gate though it also uses four transistors. Input signal A and input signal B is directly connected to the transistors Q1, Q3, and Q2, Q4. If the input signal is “HIGH” the transistors in the bottom will get saturated which will result a “LOW” output. When both inputs are “LOW” both transistors go to the cutoff region and the transistors in the top get saturated causing a “HIGH” output.
OR gate CMOS
CMOS OR gates are made by connecting an inverter circuit to the later part of the CMOS NOR gate as shown in the diagram below.
CMOS transmission gate
CMOS transmission gate is a CMOS switch that is controlled digitally using the externally applied logic levels. This transmission gate is also built using an nMOS transistor and a pMOS transistor. Both transistors are connected parallelly as shown in the diagram below. We apply complementary signals to the parallelly connected transistors. Therefore, we can use the CMOS transistor gate as a bidirectional switch.
When the signal V-control is “LOW”, CMOS transmission gates go to the high impedance state. It is when the two transistors will go to “LOW” conditions and the V1 and the V1 nodes will be open circuit. When the signal V-control is “HIGH” the two transistors will go to the “ON” state and allows a low current to pass through the V1 and the V2 nodes.
