IGBT Transistor

Transistor IGBT (Insulated Gate Bipolar Transistor) is essentially a voltage controlled power electronics device, replacing the conventional power BJTs (Bipolar Junction Transistors) and MOSFETs, as a switching devices. IGBTs are specifically designed to meet high power requirements. Although high power BJTs are available but they have low switching speed. On the other hand, high power MOSFETs are also available, have higher switching speed but can’t meet that much high power requirements.

Actually the transistor IGBT is a hybrid device made up from a FET driving a pnp BJT, and has three input terminals. The output from FET is fed to the base of BJT. This cascading results in a three terminal device that combines huge current carrying capabilities of bipolar transistor, and high switching capability of FET device These three terminals of the device are named as collector, emitter and gate. Gate is the input terminal, while emitter to collector acts as a conductive path.

IGBT – Types and internal structure

There are two types of transitor IGBT available:

• PT (punch through) – these are fabricated with and additional ”n+ layer”, called ”n+ buffer layer”,
• NPT (non punch through) – these are fabricated without ”n+ buffer layer”.

Since all the transistors are available in n-type and p-type, IGBTs are also available in both types. In this article, PT, n-channel transistor IGBT is considered.

Internal construction of the transistor IGBT consists of the following areas:

• p+ layer (Injection layer) – This is collector region. It is heavily doped. We have to apply positive voltage to make collector and buffer junction (J₃) forward biased.
• n+ layer (Buffer layer) – This is an additional layer. This layer has no effect on operation of transistor IGBT. This makes the device asymmetrical. It helps in forward breakdown region.
• n- layer (drain drift region) – This layer is lightly doped. It acts as base for PNP transistor, it is the drain of MOSFET and emitter of NPN transistor. Junction J₂ is formed between n- layer and p+ body.
• p+ (Body) – It acts as an emitter of PNP transistor, body of MOSFET and base of NPN transistor.
• n+ layer – It acts as collector of NPN transistor, source of MOSFET. Junction j₁ is formed in between p+ body and n+ layer (source)
• SiO₂ – gate is insulated by capacitance of SiO

IGBT – Principle of operation

Forward Blocking Mode – When positive voltage is applied on collector with gate and emitter shorted. Junctions J₁ and J₃ are forward biased and J₂ is reverse biased.

Conduction Mode – Apply sufficient positive voltage on gate terminal. Apply positive collector to emitter voltage. A channel of electrons is formed under SiO₂ and in p-type body region. This channel connects n+ layer to n- drift region. Transportation of electrons in n- drift region lowers the resistance of this region. Junction j₁ is also forward biased and is injecting holes into n- drift region. Holes from injection layer and electrons from n+ layer gather in drift region. The presence large number of carriers (electrons and holes) lowers the resistance of n- drift region or we can say that increases the conductivity of n- drift region. This phenomenon is called as conductivity modulation of drift region. The electrons and holes constitute the current flowing through insulated gate bipolar transistor.

Reverse Blocking Mode – When a negative voltage is applied to collector, junction j₃ is reverse biased.

IGBT – Switching characteristics

IGBT is usually used in switching applications as it operates either in cut-off or saturation region.

Specific regions of the IGBT’s output characteristic: 

V_GE=0, the device is turned off since there is no inversion layer is formed in p-type body region. This is cut-off region.

V_GE>0, V_GE<V_GET  apply V_GE  such that it is greater than 0, but less than V_GET (threshold voltage). Under this condition very little leakage current is present, which is due to the flow of minority carriers. The device is still in cut-off region. And V_CE is almost equal to V_CC.

V_GE>V_GET, the increment of gate emitter voltage beyond threshold value, put the device in active region. Due to gate emitter voltage an n-type inversion layer is created in p-type body region. Now there is a channel available for current flow.

V_GE>>V_GET, substantial increase in V_GE drives the MOSFET into the ohmic region, and the output PNP transistor into saturation region. In saturation region collector current (i_c) also increases, which decreases V_CE.

Author’s Bio:

Amna Ahmed is a passionate writer. She has been an educational blogger since 2012. She belongs to Karachi, Pakistan. She has completed her B.E. electronics engineering from a reputable institution in 2011. She loves electronics and loves to read and write anything related to electronics. She is good at writing literature reviews, lecture notes, technology reviews. Visit her blog here and stay in touch.