NewsSpirent and Cadence Partner to Streamline Networking SoC Verification

Spirent and Cadence Partner to Streamline Networking SoC Verification

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Collaborative Endeavor Between Spirent Communications and Cadence Design Systems

Spirent Communications plc, a frontrunner in the realm of testing and assurance solutions for cutting-edge devices and networks, has proclaimed a joint venture with Cadence Design Systems, Inc. This collaboration aims to offer an integrated networking system-on-chip (SoC) verification solution, seamlessly bridging the chasm between pre-silicon and post-silicon verification phases.

Revolutionizing Pre-Silicon Verification

This strategic partnership infuses unparalleled virtual Ethernet traffic emulation and testing competencies into the pre-silicon verification arena, specifically integrating with the Cadence Palladium® Z2 Enterprise Emulation and Protium™ X2 Enterprise Prototyping systems. This holistic solution not only showcases immense scalability and flexibility but also holds the prowess to emulate port speeds ranging from 1G to a whopping 800G at the application stratum. Moreover, it is adept at swiftly assimilating additional attributes, thus catalyzing the development of novel use case scenarios.

Driving Next-Gen Data Bandwidths

Forged through the combined expertise of Spirent and Cadence, this innovative solution caters to the escalating data bandwidth requisites. This is essential for verifying designs tailored for data centers and other high-end applications. By intertwining the avant-garde data rates and port densities inherent in the Spirent TestCenter, with the superlative verification proficiencies of the Cadence Palladium and Protium systems, this venture manifests as a cohesive solution. This amalgamation encompasses reusable, portable, and automated test scenarios.

Trimming the Silicon Development Lifecycle

Statements from both Spirent and Cadence resonate the mutual enthusiasm towards this collaboration. This collaboration facilitates clients with an avant-garde Chip Design Verification solution, primed to pinpoint crucial impediments early in the design lifecycle. This not only propels the time-to-market pace for the newest industry breakthroughs but also diminishes development durations. Furthermore, it streamlines the intricate Ethernet chipset design testing process, ensuring products resonate with expected performance metrics.

Key Advantages of the Unified Solution

  • Robust and efficient pre-silicon validation testing, ranging from 1G to 800G, tailored for application-level scrutiny.
  • Thorough amalgamation of the test application and emulation ecosystem, eliminating the dependence on external testing apparatus.
  • Substantial cost curtailment achieved by discerning and rectifying issues during the initial chip design phases.
  • An integrative testing platform that harmonizes pre- and post-silicon verification, fostering test continuity from inception to client deployment stages.
  • Competence to assess every stage of the silicon product lifecycle, paired with quick application reuse, standard metrics introduction for enhanced measurement, and facile integration within CI/CD frameworks.
  • Significant acceleration of the all-encompassing silicon development process.

Given the intricate nature of chip design, early-stage testing during the pre-silicon design phase can be pivotal. By identifying and mitigating issues upfront, the overall development cycle gets streamlined. The newly unveiled testing platform embodies this philosophy, ensuring a more efficient design and development journey for Ethernet chipsets.

Michal Pukala
Electronics and Telecommunications engineer with Electro-energetics Master degree graduation. Lightning designer experienced engineer. Currently working in IT industry.