Power density that is high, optimal performance, and simple usage are essential in the design of contemporary power system. To provide practical solutions to the design challenges faced by end-users in application, Infineon Technologies AG (FSE: IFX / OTCQX: IFNNY) introduces the latest version of the The OptiMOS Source-Down (SD) MOSFETs that power. They are available in the PQFN 3.3 3.0 x 3.3 millimeter 2 package, and have a voltage class that spans 25 V the 100-volt range. This device sets new standards in performance of power MOSFETs by providing higher efficiency, better power density, better thermal management and a lower bills-of-material (BOM). The PQFN can be used for motor drivesand SMPS, telecom and server applications, OR-ing, and the battery management system.
In comparison to the traditional Drain-Down design, most recent Source-Down package technology permits an even larger silicon die inside the same package. Additionally, the loss that the package causes, which limit your device’s overall effectiveness can be minimized. This can result in a reduction of the rate of DS(on) by as much as 30 percent when compared to the current Drain-Down device. The advantage on a system-wide level is the reduction in the form factor , and the option of moving from a SuperSO8 5-x 6 millimeter footprint to the PQFN 3.3 2 3.3 millimeter 2 package that has an area reduction of approximately 65 percent. This permits the space to be utilized efficiently, increasing the power density as well as the system efficiency at the end of the day.
Furthermore, in the Source-Down design, the heat is absorbed directly into the PCB via the thermal pad rather than via the wire that connects to it or copper clip. This increases its heat resistance R thJC by over 20 percent up from 1.8 K/W to 1.4 K/W, thereby enabling an easier thermal management. Infineon has two designs and layouts including the SD Standard-Gate and the center-Gate version of the SD. The Standard-Gate layout facilitates the drop-in replacement for Drain-Down products while the layout for the Center-Gate allows for a more efficient and simpler parallelization. Both layouts can provide optimal arrangement of devices on the PCB, improved PCB parasitics, as well as user-friendliness.