The recently released Universal Chiplet Interconnect Express (UCIe) 1.0 specification addresses the physical layer of die-to-die I/O as well as die-to-die protocols. an application stack model that makes use of PCI Express (PCIe) and Compute Express Link (CXL) industry standards.
It’s safe to say that UCIe is an extremely long way off. Chiplets aren’t new, however, the the recent increase in enthusiasm for the technology is raising questions regarding the necessity of a norm and the best practice.
UCIe has been the subject of lots of attention in recent times due to its proven-to-be-true design and capability to assist companies in the field of semiconductors solve problems that they face with today. Chiplets provide a method of integrated design and development of semiconductors that has the potential of speeding up things by leveraging Moore’s Law, which is more than 60 years old. The speed of advancement in semiconductor manufacturing has been slowing since late.
Chiplets have the potential to bring back the two-year doubling cycle that has been the basis of the semiconductor industry since the year 1965. They replace one silicon die with a number of smaller dies as an integrated package, which allows more silicon to include transistors.
“A lot of the companies are hitting against the critical limit in their design as the demand for processing continues to be insatiable,” said UCIe chair and Intel senior member Debendra Das Sharma. “So different companies are putting together their own chiplet connected through their own proprietary mechanism, effectively offering a scale-up solution.”
In addition to being able to reduce size and improve yields simultaneously they are attractive because they are built with known and tested techniques and components. This decreases the chance of failure due due to advancements in packaging and testing. Another advantage of using chiplets is that they allow companies to sew together dies from different manufacturers, allowing them to concentrate on their strengths when creating devices.
They also have the highest quality for the money since it’s not necessary to always go to the next node. A chiplet may comprise the die in a single piece that’s made in sixty nanometers (nm) and the other at 28 nanometers, which allows the flexibility as well as reliability.
The additional flexibility offered by chips is, however, a sign that companies approach chiplet design in a different manner. Prior to the release of UCIe 1.0 standard in the year 2000, chiplets were a part of the Open Compute Project (OCP) was working on gathering best practices using an OCP Open Domain-Specific Architecture sub-project, which aimed to develop common procedures for making chiplets.
Manufacturer of computer hardware zGlue is another company seeking to provide clarity to the chiplet industry. It provides a platform and method for creating custom chips to assist hardware manufacturers in responding to ever-increasing time-to-market pressures.
The purpose of the UCIe 1.0 specification is the same: integrate the semiconductor industry on an open platform that allows chiplet-based solutions that build an ecosystem of chiplets which allows heterogeneous integration and thus preserving the ability to mix and match chips from various processes, fabs and suppliers.
“Heterogeneous chiplet integration is needed to get a lot of the economies of scale,” Das Sharma said. “It reduces your time-to-market by reusing existing chiplets.”
The UCIe 1.0 specification was adopted to offer a comprehensive standard die-to-die interconnect that includes a physical layer and protocol stack, a software model and compliance testing. This will allow end users to integrate elements from a multi-vendor marketplace for system-on chip (SoC) development. “This is going to be a game changer in the entire industry,” Das Sharma stated. “This is how people are going to be building their SoCs.”
Das Sharma went on to clarify the mission of the UCIe consortium is to ensure that it is that the UCIe 1.0 standard provides impressive power, performance and cost features. “We are looking to be capable of moving a significant amount of bandwidth in an extremely efficient manner. You can design a system that will provide lots of bandwidth at very low latencyand with a low cost and with a minimal power consumption.”
Interoperability is also important and requires clarity about how things are expected to function. “We must ensure that we’re creating the complete stack. If we’re looking to make it easy to use and we’re looking to make use of existing software because we don’t want and make a fresh start.”
The companies that are currently participating in the committee that is managing the UCIe include AMD, Google, Meta, Microsoft, Samsung, and TSMC. Intel plays a major role in the process by “donating” the initial specification.
The CXL/PCIe standard was chosen as protocols due to the fact that they’re interfaces for boards and will address the common usage cases. PCIe/CXL.io handle attaching I/O devices, CXL.mem handles memory use scenarios as well as CXL.cache handles accelerator usage scenarios. Similar to the PCIe as well as CXL, UCIe is focused on interoperability, even as it develops. Das Sharma said other protocols are in the pipeline for future versions and also advanced chiplet form factors as well as chiplet control.
Intel considers UCIe as an essential element to their IDM 2.0 strategy according to Kurt Lender, IO Technology Solution Team Strategist within Intel’s AI and datacenter group. This is because the standard relies on Intel’s open and Advanced Interface Bus standard, and allows the use of the correct chiplet for the job regardless of who is the one who develops the chip, Lender wrote in a recent blog article.
“It’s a new era of semiconductor architecture that puts designers in control and continues Moore’s vision of doubling computing power well into the foreseeable future.”